/*********************************************************************/
/*                                                                   */
/*      SVPWM Driver                                                 */
/*                                                                   */
/*      Last updated by:  CBS                                        */
/*      Last update date: 12/12/25                                   */
/*      Revision:         0                                          */
/*      Copyright:        DENSO                                      */
/*                                                                   */
/*********************************************************************/

/*********************************************************************/
/*  include files                                                    */
/*********************************************************************/
#include "Svpwm.h"

/*********************************************************************/
/*  prototypes                                                       */
/*********************************************************************/

/*********************************************************************/
/*  defines / data types / structs / unions / macros                 */
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/*********************************************************************/
/*  constants                                                        */
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const Svpwm_ConfigType SvpwmConfig =                     /* SVPWM09a */
{
    
    { 
        {
        {(U4)(65 ), \
         (U4)(459), \
         (U4)0x0000,\
         (U4)0x0, /* FREN:Freeze Enable Bit 0:Normal 1:Freeze        */
         (U4)0x0, /* ODIS:Output Disable Bit 0:Normal 1:Output EDPOL */
         (U4)0x3, /* ODISSL:Output Disable Select Bit                */
         (U4)0x0, /* UCPRE:Prescaler Bits 00:1 11:4                  */
         (U4)0x1, /* UCPREN:Prescaler Bit 0:Disabled 1:Enabled       */
         (U4)0x0, /* DMA:Direct Memory Access Bit 0:Interrupt 1:DMA  */
         (U4)0x0, /* Reserverd                                       */
         (U4)0x0, /* IF:Input Filter Bits No meaning for output mode */
         (U4)0x0, /* FCK:Filter Clock Select Bit 0:Prescaled 1:Main  */
         (U4)0x0, /* FEN:FLAG Enable Bit  0:Disable 1:Enable         */
         (U4)0x0, /* Reserved                                        */
         (U4)0x1, /* FORCMA:Force Match A Bit 0:No effect 1:Match    */
         (U4)0x1, /* FORCMB:Force Match B Bit 0;No effect 1:Match    */
         (U4)0x0, /* Reserved                                        */
         (U4)0x3, /* BSL:Bus Select Bits 11:Internal counter         */
         (U4)0x1, /* EDSEL:Edge Selection Bit Not Effect             */
         (U4)0x1, /* EDPOL;Edge Polarity Bit 0:LOW 1:HIGH            */
         (U4)0x21 /* MODE 0x21:OPWM                                  */
         },\
         (U2)SVPWM_CHANNEL_0                           /* Duty = 75% */
        },  
        {
        {(U4)(65 - SVPWM_PHASE_DELAY), \
         (U4)(459),                    \
         (U4)0x0000,                   \
         (U4)0x0, /* FREN:Freeze Enable Bit 0:Normal 1:Freeze        */
         (U4)0x0, /* ODIS:Output Disable Bit 0:Normal 1:Output EDPOL */
         (U4)0x3, /* ODISSL:Output Disable Select Bit                */
         (U4)0x0, /* UCPRE:Prescaler Bits 00:1 11:4                  */
         (U4)0x1, /* UCPREN:Prescaler Bit 0:Disabled 1:Enabled       */
         (U4)0x0, /* DMA:Direct Memory Access Bit 0:Interrupt 1:DMA  */
         (U4)0x0, /* Reserverd                                       */
         (U4)0x0, /* IF:Input Filter Bits No meaning for output mode */
         (U4)0x0, /* FCK:Filter Clock Select Bit 0:Prescaled 1:Main  */
         (U4)0x0, /* FEN:FLAG Enable Bit  0:Disable 1:Enable         */
         (U4)0x0, /* Reserved                                        */
         (U4)0x1, /* FORCMA:Force Match A Bit 0:No effect 1:Match    */
         (U4)0x1, /* FORCMB:Force Match B Bit 0;No effect 1:Match    */
         (U4)0x0, /* Reserved                                        */
         (U4)0x3, /* BSL:Bus Select Bits 11:Internal counter         */
         (U4)0x1, /* EDSEL:Edge Selection Bit Not Effect             */
         (U4)0x0, /* EDPOL;Edge Polarity Bit 0:LOW 1:HIGH            */
         (U4)0x21 /* MODE 0x21:OPWM                                  */
         },\
         (U2)SVPWM_CHANNEL_1
        },
        {
        {(U4)(131),  \
         (U4)(394),  \
         (U4)0x0000, \
         (U4)0x0, /* FREN:Freeze Enable Bit 0:Normal 1:Freeze        */
         (U4)0x0, /* ODIS:Output Disable Bit 0:Normal 1:Output EDPOL */
         (U4)0x3, /* ODISSL:Output Disable Select Bit                */
         (U4)0x0, /* UCPRE:Prescaler Bits 00:1 11:4                  */
         (U4)0x1, /* UCPREN:Prescaler Bit 0:Disabled 1:Enabled       */
         (U4)0x0, /* DMA:Direct Memory Access Bit 0:Interrupt 1:DMA  */
         (U4)0x0, /* Reserverd                                       */
         (U4)0x0, /* IF:Input Filter Bits No meaning for output mode */
         (U4)0x0, /* FCK:Filter Clock Select Bit 0:Prescaled 1:Main  */
         (U4)0x0, /* FEN:FLAG Enable Bit  0:Disable 1:Enable         */
         (U4)0x0, /* Reserved                                        */
         (U4)0x1, /* FORCMA:Force Match A Bit 0:No effect 1:Match    */
         (U4)0x1, /* FORCMB:Force Match B Bit 0;No effect 1:Match    */
         (U4)0x0, /* Reserved                                        */
         (U4)0x3, /* BSL:Bus Select Bits 11:Internal counter         */
         (U4)0x1, /* EDSEL:Edge Selection Bit Not Effect             */
         (U4)0x1, /* EDPOL;Edge Polarity Bit 0:LOW 1:HIGH            */
         (U4)0x21 /* MODE 0x21:OPWM                                  */
         },\
         (U2)SVPWM_CHANNEL_2                           /* Duty = 50% */
        },
        {
        {(U4)(131 - SVPWM_PHASE_DELAY),\
         (U4)(394),                    \
         (U4)0x0000,                   \
         (U4)0x0, /* FREN:Freeze Enable Bit 0:Normal 1:Freeze        */
         (U4)0x0, /* ODIS:Output Disable Bit 0:Normal 1:Output EDPOL */
         (U4)0x3, /* ODISSL:Output Disable Select Bit                */
         (U4)0x0, /* UCPRE:Prescaler Bits 00:1 11:4                  */
         (U4)0x1, /* UCPREN:Prescaler Bit 0:Disabled 1:Enabled       */
         (U4)0x0, /* DMA:Direct Memory Access Bit 0:Interrupt 1:DMA  */
         (U4)0x0, /* Reserverd                                       */
         (U4)0x0, /* IF:Input Filter Bits No meaning for output mode */
         (U4)0x0, /* FCK:Filter Clock Select Bit 0:Prescaled 1:Main  */
         (U4)0x0, /* FEN:FLAG Enable Bit  0:Disable 1:Enable         */
         (U4)0x0, /* Reserved                                        */
         (U4)0x1, /* FORCMA:Force Match A Bit 0:No effect 1:Match    */
         (U4)0x1, /* FORCMB:Force Match B Bit 0;No effect 1:Match    */
         (U4)0x0, /* Reserved                                        */
         (U4)0x3, /* BSL:Bus Select Bits 11:Internal counter         */
         (U4)0x1, /* EDSEL:Edge Selection Bit Not Effect             */
         (U4)0x0, /* EDPOL;Edge Polarity Bit 0:LOW 1:HIGH            */
         (U4)0x21 /* MODE 0x21:OPWM                                  */
         },\
         (U2)SVPWM_CHANNEL_3
        },
        {
        {(U4)(197 ),\
         (U4)(328 ),\
         (U4)0x0000,\
         (U4)0x0, /* FREN:Freeze Enable Bit 0:Normal 1:Freeze        */
         (U4)0x0, /* ODIS:Output Disable Bit 0:Normal 1:Output EDPOL */
         (U4)0x3, /* ODISSL:Output Disable Select Bit                */
         (U4)0x0, /* UCPRE:Prescaler Bits 00:1 11:4                  */
         (U4)0x1, /* UCPREN:Prescaler Bit 0:Disabled 1:Enabled       */
         (U4)0x0, /* DMA:Direct Memory Access Bit 0:Interrupt 1:DMA  */
         (U4)0x0, /* Reserverd                                       */
         (U4)0x0, /* IF:Input Filter Bits No meaning for output mode */
         (U4)0x0, /* FCK:Filter Clock Select Bit 0:Prescaled 1:Main  */
         (U4)0x0, /* FEN:FLAG Enable Bit  0:Disable 1:Enable         */
         (U4)0x0, /* Reserved                                        */
         (U4)0x1, /* FORCMA:Force Match A Bit 0:No effect 1:Match    */
         (U4)0x1, /* FORCMB:Force Match B Bit 0;No effect 1:Match    */
         (U4)0x0, /* Reserved                                        */
         (U4)0x3, /* BSL:Bus Select Bits 11:Internal counter         */
         (U4)0x1, /* EDSEL:Edge Selection Bit Not Effect             */
         (U4)0x1, /* EDPOL;Edge Polarity Bit 0:LOW 1:HIGH            */
         (U4)0x21 /* MODE 0x21:OPWM                                  */
         },\
         (U2)SVPWM_CHANNEL_4                           /* Duty = 25% */
        },
        {
        {(U4)(197 - SVPWM_PHASE_DELAY),\
         (U4)(328),                    \
         (U4)0x0000,                   \
         (U4)0x0, /* FREN:Freeze Enable Bit 0:Normal 1:Freeze        */
         (U4)0x0, /* ODIS:Output Disable Bit 0:Normal 1:Output EDPOL */
         (U4)0x3, /* ODISSL:Output Disable Select Bit                */
         (U4)0x0, /* UCPRE:Prescaler Bits 00:1 11:4                  */
         (U4)0x1, /* UCPREN:Prescaler Bit 0:Disabled 1:Enabled       */
         (U4)0x0, /* DMA:Direct Memory Access Bit 0:Interrupt 1:DMA  */
         (U4)0x0, /* Reserverd                                       */
         (U4)0x0, /* IF:Input Filter Bits No meaning for output mode */
         (U4)0x0, /* FCK:Filter Clock Select Bit 0:Prescaled 1:Main  */
         (U4)0x0, /* FEN:FLAG Enable Bit  0:Disable 1:Enable         */
         (U4)0x0, /* Reserved                                        */
         (U4)0x1, /* FORCMA:Force Match A Bit 0:No effect 1:Match    */
         (U4)0x1, /* FORCMB:Force Match B Bit 0;No effect 1:Match    */
         (U4)0x0, /* Reserved                                        */
         (U4)0x3, /* BSL:Bus Select Bits 11:Internal counter         */
         (U4)0x1, /* EDSEL:Edge Selection Bit Not Effect             */
         (U4)0x0, /* EDPOL;Edge Polarity Bit 0:LOW 1:HIGH            */
         (U4)0x21 /* MODE 0x21:OPWM                                  */
         },\
         (U2)SVPWM_CHANNEL_5
        }
    },
    #if SVPWM_NOTIFICATION_SUPPORTED == STD_ON
    {
        NotificationHandlers[SVPWM_NUMBER_OF_CHANNELS];
    }
    #endif/* SVPWM_NOTIFICATION_SUPPORTED */
};

/*********************************************************************/
/*  variables                                                        */
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/* Configuration Pointer Initialization */
static const Svpwm_ConfigType* ConfigPtr = &SvpwmConfig; 

/**** End Of File ****************************************************/